A distinction is made between flip-flops, which are controlled by a rising or falling edge, and pulsed latches, which are controlled by a pulsed signal.
In order to control a flip-flop, a control signal, such as a clock signal, is distributed to each flip-flop by a clock tree comprising latches. The dimensions of this clock tree are chosen to respect certain synchronisation constraints of the control signal at the input of each flip-flop.
Pulsed latches are less complex than flip-flops, and thus allow more compact circuit designs and reduced power consumption. Data is input to a pulsed latch during a high pulse of a pulsed timing signal. The pulsed timing signal is generated by a pulse generator, and each of the pulses generally has a pulse width significantly shorter than the high or low periods of a normal clock signal.
Whereas today synchronous circuits generally use flip-flops as the synchronisation elements, for the above reasons it would be desirable to replace the flip-flops by pulsed latches. However, during the conception of the clock tree, digital circuit implementation tools are adapted to perform timing analysis based on propagation of clock edges rather than an analysis based on pulses, and they often do not allow the insertion of pulse generators. There is thus a problem in the conception and verification of circuit designs based on pulsed latches.